1. Field of the Invention
The present invention generally relates to ferroelectric dielectrics and more specifically to a ferroelectric capacitor that is annealed before the bitline is formed and which is formed over the active area to reduce the size of the memory cell.
2. Description of the Related Art
Ferroelectric dielectrics are being actively investigated for use in a non-volatile memory devices and high-dielectric materials are being actively investigated for use in DRAM (Dynamic Random Access Memory) devices. In such devices, a capacitor is fabricated by depositing a thin film of a ferroelectric material such as SrBi.sub.2 Ta.sub.2 O.sub.9 (SBT),Pb(Zr,Ta)O.sub.3 (lead zirronate titanate), or their many variations, or a high-dielectric material such as (Ba,Sr)TiO.sub.3 (KST) between 2 electrodes. The electrodes are either noble metals (Ir, Pt, Ru, Pd, Au) or noble metal oxides (RuO.sub.2,IrO.sub.2, . . . ). In the completed device, one electrode is connected to a transfer device while the other electrode serves as a common reference plate or a drive line.
More specifically, FIG. 1 illustrates an N-type substrate 10 having a N+ diffusion region 11, an insulating layer 12 and a polysilicon plug 13 within the insulating layer 12. Further, the structure shown and FIG. 1 includes a barrier layer 14, top and bottom electrodes 15, the ferroelectric l6 and an insulator 17.
FIG. 2 illustrates a bit line 20, a word line 21, a tungsten plug 22, a top electrode 23 and a bottom electrode 24 on either side of a ferroelectric 25. The tungsten plug 22 is connected to the top electrode 23 by a local interconnect 26.
One problem that occurs when fabricating such conventional devices is the high temperature anneal required to form the correct phase of the ferroelectric dielectric. This anneal typically requires a temperature of 700-850.degree. C. in an oxidizing ambient. Since the noble metal or noble metal oxide electrodes are not good diffusion barriers for oxygen, any conductor connected to the electrode will have a tendency to be oxidized during this anneal. Therefore, such conventional structures are very difficult to produce and have a high defect rate associated with the high-temperature anneal.
For example, with the structure shown in FIG. 1, the conductor 13 is below the ferroelectric 16 and must be formed before the ferroelectric 16. Therefore, during the anneal of the ferroelectric the conductor 13 may be oxidized, which reduces the electrical conductivity between the electrodes 15 and the conductor 13, decreases device performance and increases defect rates.
While the local interconnect 26 shown in FIG. 2 is positioned above the top electrode 23 and can be formed after the ferroelectric 25 is annealed, the capacitor 25 is not formed over the device 21 resulting in a large cell size.
The invention overcomes the foregoing problems by forming the ferroelectric in a processed which avoids oxidation of the conductive paths to the electrodes of the ferroelectric capacitor, and still provides a small cell size, as discussed in greater detail below.